vhdl - How to deal with signed numbers correctly and still use "+" -

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity alu_16     port ( : in  std_logic_vector(15 downto 0);            b : in  std_logic_vector(15 downto 0);            sel : in  std_logic_vector (1 downto 0);            gt : out  std_logic;            lt : out  std_logic;            eq : out  std_logic;            result : out  signed(15 downto 0);            overflow : out  std_logic;            cout : in  std_logic); end alu_16;  architecture behavioral of alu_16     signal inter_res : signed(16 downto 0);     signal subtraction : signed(16 downto 0);     signal addition : signed (16 downto 0);     signal carry_in : std_logic;     signal carry_out : std_logic;     signal msb_bit_add : std_logic; begin     gt <= '1' when > b else '0';     lt <= '1' when < b else '0';     eq <= '1' when = b else '0';     subtraction <= signed(a) - signed(b);     addition <= signed(a) + signed(b);     sel select      inter_res <= addition when "00",                   subtraction when "01",                  signed(a) , signed(b) when "10",                  signed(a) or  signed(b) when others;     carry_out <= inter_res(16);     msb_bit_add <= std_logic(a(15) + b(15));     carry_in <= msb_bit_add xor inter_res(15);     overflow <= not(carry_in xor carry_out);     result <= inter_res(15 downto 0);     end behavioral; 

so.. i'm trying make 16 bit signed adder without using ripple carry adder. however, getting errors overloading + operator @ 1 bit add msb_bit_add. can shed light on should on line?

thanks!