vhdl - Directly indexing a bit of an arithmetic result -

for issue, consider have following signals , using synopsis packages std_logic_unsigned , std_logic_arith.

signal o : std_logic; signal  : std_logic_vector(parameter downto 0); constant c : integer := 5; 

i wish set o signal leftmost bit of result of (i-c). inside of process have like:

o <= (i-c)(i'left); 

which not compile in simulator.

i know can solve introducing intermediary variable, there syntactic construct directly?

you trying assign o indexed name value result of expression.

a indexed name prefix can either name or function call.

 indexed_name ::=  prefix ( expression { , expression } )   prefix ::=          name      | function_call 

functions expressions predefined attributes, e.g. i'length or i'left.

a function call has specific format:

 function_call ::=     function_name [ ( actual_parameter_part ) ]   actual_parameter_part ::=  parameter_association_list  

keeping in mind using package numeric_std (in case without numeric_std_unsigned) gives:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity indexing     constant parameter: natural :=7; end entity;  architecture foo of indexing     signal o : std_logic;     signal  : signed(parameter downto 0);     constant c : integer := 5; begin      o <= "-"(i,to_signed(c,i'length)) (i'left);  end architecture; 

and of course use type conversions in association list "-" function call association list,

type signed selected because constant c specified type integer. have been type unsigned, or std_logic_vector using package numeric_std_unsigned. selecting type signed in part whimsical, o specifies result sign way.

the above example analyzes, elaborates , runs, not doing interesting, while demonstrating syntax valid.

slice names can manipulated.

(and yes work synopsys's package std_logic_unsigned, without type conversions , specifying i type std_logic_vector. there's little advantage when using function call.)